EDN

Cisco taps processor array architecture for NPU

San Mateo, Calif. – Single-chip systems based on a large array of CPU cores are quietly appearing in an increasing number of applications. Design teams are finding that these architectures, though far ...
Network World

Cray to unite scalar, vector computer architectures

Cray plans to create a new supercomputing platform combining four types of processing capability in a blade server architecture. Cray Inc. plans to create a new supercomputing platform combining four ...
Semiconductor Engineering

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)

A new technical paper titled “MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference” was published by researchers at FZI Research Center for Information ...
EDN

Putting a polyphase filter in processor array

While most articles in this section discuss the reprogramming of graphics processors, other large arrays of processing elements are available as standard-product ICs for other applications. In some ...
Business Wire

SiFive Intelligence for Modern ML Architectures Presentation at Linley Spring Processor Conference

SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Chris Lattner, President of Engineering and ...
Android Authority

Armv9 heralds the next-generation of smartphone CPUs

Every processor ever built contains an underlying “architecture,” representing deep-seated characteristics that transcend any single CPU core or physical design. This architecture defines how a ...