Electronic Design

Should Dual Rail Go Mainstream in Deep Nanometer Era?

Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the ...
Design-Reuse

Embedded SRAM test and repair moves on-chip

SAN MATEO, Calif. — With the rollout of its Star Memory System, an on-chip test and repair mechanism for embedded SRAM, memory compiler specialist Virage Logic Corp. is making good on its promise to ...
Design-Reuse

sureCore Delivers Customised Low Power SRAM for Data Intensive Designs

SHEFFIELD, England, Mar. 21, 2019 – sureCore Limited's new SureFit SRAM customization service has delivered low power high capacity SRAM subsystems implemented in advanced FinFET processes to Tier-1 ...