Semiconductor Engineering

Are You Using Structural Patterns In An SLT Environment?

Patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding ...
Semiconductor Engineering

Better ATPG To Minimize Chip Test Time And Cost

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, ...
Electronic Design

What’s The Difference Between Scan ATPG And IJTAG Pattern Retargeting?

Both scan automated test pattern generation (ATPG) patterns and IJTAG patterns 1,2,3 are created for a piece of logic that is part of a much larger design. For both, the patterns are independent from ...
EDN

Decreasing Cost-of-Test with Automatic Test-Pattern Generation

Success in the electronics business hinges on producing high-quality products and using the most cost-effective methods to do so. As the number of devices on ICs continues to double every 18 to 24 ...
Electronic Design

ATPG Tool Delivers Design-For-Test Solution

In its latest version, FastScan 2001 automatic test pattern generation (ATPG) tool reportedly can reduce test pattern sizes by as much as 60%. It can also test small embedded memories and other macros ...
EDN

Decreasing the Cost of Test with Automatic Test Pattern Generation

Success in the electronics business hinges on producing high-quality products and using the most cost-effective methods to do so. As the number of devices on integrated circuits continues to double ...